I. Field of the Invention
The present invention relates to a semiconductor structure applicable to semiconductor devices, such as MOSFET""s (insulated gate field effect transistors), IGBT""s (insulated gate bipolar transistors), bipolar transistors and diodes. Specifically, the present invention relates to a semiconductor structure, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device to realize a high breakdown voltage and a high current capacity.
II. Description of Related Art
The semiconductor devices may be classified into a lateral device, which has main electrodes thereof arranged on one major surface with a drift current flow parallel to the major surface, and a vertical device, which has the main electrodes thereof distributed on two major surfaces facing opposite to each other and a drift current flow perpendicular to the major surfaces. In the vertical semiconductor device, the drift current flows in the thickness direction of the semiconductor chip (vertically) in the ON-state of the semiconductor device and depletion layers expand also in the thickness direction of the semiconductor chip (vertically) in the OFF-state of the semiconductor device. In the conventional vertical planar-type n-channel MOSFET, the very resistive n-type drift layer thereof provides a drift current path in the ON-state of the MOSFET and is depleted in the OFF-state thereof, resulting in a high breakdown voltage.
Thinning the n-type drift layer, that is shortening the drift current path, facilitates a substantial reduction in the on-resistance, since the drift resistance against the drift current flow is reduced. However, thinning the n-type drift layer narrows the separation width between the drain and the base, limiting the expansion of the depletion layers of the pn-junctions between p-type base regions and the n-type drift layer. Due to the narrow expansion width of the depletion layers, the electric field strength soon reaches the critical value for silicon. Therefore, breakdown is caused at a voltage lower than the designed breakdown voltage of the device. A high breakdown voltage is obtained by increasing the thickness of the n-type drift layer. However, the thick n-type drift layer inevitably causes high on-resistance that further causes loss increase. In other words, there exists a tradeoff relation between the on-resistance and the breakdown voltage.
The tradeoff relation between the on-resistance and the breakdown voltage exists in the other semiconductor devices such as IGBT""s, bipolar transistors and diodes. The tradeoff relation also exists in the lateral semiconductor devices, in that the flow direction of the drift current in the ON-state of the device and the expansion direction of the depletion layers by applying a reverse bias voltage in the OFF-state of the device are different from each other. European Patent 0 053 854, U.S. Pat. Nos. 5,216,275, 5,438,215, and Japanese Unexamined Laid Open Patent Application H09-266311 disclose semiconductor devices, which facilitate reducing the tradeoff relation between the on-resistance and the breakdown voltage. The drift layers of the disclosed semiconductor devices are formed of alternating conductivity type layers including heavily doped n-type regions and heavily doped p-type regions. The alternating conductivity type layer, depleted in the OFF-state, facilitates sustaining a high breakdown voltage.
The drift layer of the every disclosed semiconductor device is not a uniform impurity diffusion layer of one conductivity type but an alternating conductivity type layer formed of thin n-type drift regions and thin p-type partition regions laminated alternately. The n-type drift regions and p-type partition regions are shaped with respective thin layers extending vertically. Since the entire drift layer is occupied by the depletion layers expanding laterally from the vertically extending pn-junctions between n-type drift regions and p-type partition regions in the OFF-state of the MOSFET, a high breakdown voltage is obtained even when the impurity concentrations in the n-type drift regions and the p-type partition regions are high.
Japanese Unexamined Laid Open Patent Application No. 2000-40822 discloses the method of manufacturing such a semiconductor device including an alternating conductivity type layer. FIG. 8 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to FIG. 8, the vertical MOSFET includes a drift layer 12, that is not a uniform layer but is formed of n-type drift regions 12a and p-type partition regions 12b arranged alternately. In the figure, p-type well regions 13, n+-type source regions 14, gate insulation films 15, gate electrode layers 16, a source electrode 17 and a drain electrode 18 are shown.
The alternating-conductivity-type drift layer 12 is formed by the epitaxially growing a very resistive n-type layer on an n++-type drain layer 11 used for a substrate, by selectively etching trenches in the n-type layer, leaving n-type drift regions 12a, and by epitaxially growing p-type partition regions 12b in the trenches. Hereinafter, the semiconductor device including an alternating conductivity type layer, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device, will be referred to as the xe2x80x9csuper-junction semiconductor devicexe2x80x9d.
The foregoing publications describe active regions including an alternating conductivity type layer, through which a drift current flows. However, the foregoing publications describe almost nothing on the breakdown withstanding region, usually disposed around the active region to realize a high breakdown voltage. For realizing a practical semiconductor device exhibiting a high breakdown voltage, it is necessary to design the semiconductor structure based on the consideration of the breakdown voltage.
For example, when the thickness of the alternating conductivity type layer in the active region and the thickness thereof in the breakdown withstanding region are the same, a voltage is applied evenly to the n-type drift regions and the p-type partition regions of the alternating conductivity type layer. As a result, depletion layers expand vertically, and the electric field in the active region is relaxed in proportion to the thickness of the alternating conductivity type layer. In the breakdown withstanding region, the surface electric field parallel to the major surface is relaxed by employing a field plate structure or a guard ring structure. However, depletion layers do not expand so widely in the breakdown withstanding region as compared with in the active region. Therefore, the electric field in the breakdown withstanding region is denser than the electric field in the active region. Therefore, the electric field strength in the breakdown withstanding region reaches the critical value sooner than the electric field strength in the active region. As a result, the breakdown withstanding region determines the breakdown voltage of the semiconductor device.
Since the electric field strength in the breakdown withstanding region reaches the critical value sooner than the electric field strength in the active region, an avalanche current is caused in the breakdown withstanding region. The avalanche current, that localizes to the outer p-type region in the active region, makes a parasitic transistor work. Thus, breakdown is caused in the super-junction semiconductor device and the reliability of the super-junction semiconductor device is impaired, Moreover, it is difficult to maintain an avalanche withstanding capability (breakdown withstanding capability) of the super-junction semiconductor device under an inductive load (hereinafter referred to as an xe2x80x9cL-loadxe2x80x9d).
In view of the foregoing, it would be desirable to provide a very reliable super-junction semiconductor device, that facilitates relaxing tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an L-load.
According to a first aspect of the invention, there is provided a semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; a first main electrode on the first major surface; a second main electrode on the second major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer formed of first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type arranged alternately at a first pitch of repeating; a second alternating conductivity type layer formed of third semiconductor regions of the first conductivity type and fourth semiconductor regions of the second conductivity type arranged alternately at a second pitch of repeating; the first alternating conductivity type layer and the second alternating conductivity type layer being between the first major surface and the layer with low electrical resistance; and the thickness of the first alternating conductivity type layer and the thickness of the second alternating conductivity type layer being different from each other.
Advantageously, the second alternating conductivity type layer is thicker than the first alternating conductivity type layer, and the second alternating conductivity type layer is around the first alternating conductivity type layer. When the second alternating conductivity type layer in the breakdown withstanding region is thicker than the first alternating conductivity type layer in the active region, the electric field strength in the breakdown withstanding region is relaxed more than the electric field strength in the active region and, therefore, the electric field strength in the active region reaches the critical value in advance of the electric field strength in the breakdown withstanding region. Therefore, the breakdown voltage of the device is determined by the structure of the active region. Since an avalanche current is caused not in the breakdown withstanding region but in the active region, the avalanche current does not localize to the peripheral portion of the active region. Therefore, the reliability and the avalanche withstanding capability under an L-load of the super-junction semiconductor device are improved. Since the first alternating conductivity type layer in the active region according to the invention is thinner than the conventional alternating conductivity type layers, the drift current path length is shortened and, therefore, the on-resistance is reduced.
According to a second aspect of the invention, there is provided a semiconductor device including a very resistive region, the specific resistance thereof is high, of the first conductivity type or the second conductivity type around the first alternating conductivity type layer or around the second alternating conductivity type layer, the very resistive region being thicker than the first alternating conductivity type layer.
According to a third aspect of the invention, there is provided a semiconductor device including a third alternating conductivity type layer between the first alternating conductivity type layer and the layer with low electrical resistance, the third alternating conductivity type layer being formed of fifth semiconductor regions of the first conductivity type and sixth semiconductor regions of the second conductivity type arranged alternately at the first pitch of repeating, the impurity concentrations in the fifth semiconductor regions and the sixth semiconductor regions and the impurity concentrations in the first and second semiconductor regions being different from each other.
Advantageously, the impurity concentrations in the fifth semiconductor regions and the sixth semiconductor regions are higher than the impurity concentrations in the first semiconductor regions and the second semiconductor regions. Advantageously, the impurity concentration in the fifth semiconductor regions or the impurity concentration in the sixth semiconductor regions is higher than the impurity concentration in the first semiconductor regions or the second semiconductor regions. Since in certain semiconductor regions, the impurity concentration thereof are high, of the third alternating conductivity type layer in the active region suppress depletion layer expansion, the electric field strength is raised and the electric field strength in the active region reaches the critical value in advance of the electric field strength in the breakdown withstanding region.
Advantageously, the second pitch of repeating is narrower than the first pitch of repeating. Advantageously, the impurity concentrations in the second alternating conductivity type layer are lower than the impurity concentrations in the first alternating conductivity type layer or the impurity concentrations in the third alternating conductivity type layer. Since the structures described above facilitate relaxing the electric field in the breakdown withstanding region more easily than the electric field in the active region, the electric field strength in the active region reaches the critical value in advance of the electric field strength in the breakdown withstanding region and an avalanche current flows in the active region in advance.
Advantageously, the semiconductor device further includes a heavily doped intermediate semiconductor layer of the first conductivity type between the first alternating conductivity type layer and the layer with low electrical resistance. The heavily doped intermediate semiconductor layer of the first conductivity type facilitates suppressing depletion layer expansion therein and raising the electric field strength in the active region. Advantageously, the impurity concentration in the intermediate semiconductor layer is higher than the impurity concentration in the first semiconductor regions in the first alternating conductivity type layer. This impurity concentration profile facilitates suppressing depletion layer expansion in the intermediate semiconductor layer more effectively.
The very resistive region around the first alternating conductivity type layer or around the second alternating conductivity type layer, which can be of either the first conductivity type or the second conductivity type, promotes depletion layer expansion in the very resistive region and reduces the electric field strength in the breakdown withstanding region. Advantageously, the impurity concentration ND in the very resistive region and the breakdown voltage VDSS (V) of the semiconductor device are related to each other by the following expression.
xe2x80x83NDxe2x89xa65.62xc3x971017xc3x97VDSSxe2x88x921.36(cmxe2x88x923)
German Patent Application DE 19 954 351A1 discloses that it is effective to control the specific resistance of the breakdown withstanding region by adjusting the impurity concentration as expressed by the above expression. The above expression is effectively applicable also to the semiconductor device including a heavily doped intermediate layer of the first conductivity type or a heavily doped third alternating conductivity type layer interposed between the first alternating conductivity type layer and the layer with low electrical resistance.
Advantageously, the semiconductor device further includes a channel stopper region of either first conductivity type or the second conductivity type around the very resistive region. The channel stopper region disposed around the very resistive region stabilizes the breakdown voltage and improves the reliability of the device.